Lab 5 - EE 421L 

Authored by Steven Leung,

leungs@unlv.nevada.edu

9/28/2015

  

Pre-lab work


Lab description

    This lab involves designing a laying out 2 different size inverters, one 12u/.6u and the other 48u/2.4u for the PMOS. We will then look at the differences in these two inverters to see which one performs better. 

 

 

 Below include the schematic views for the inverters.


12u/.6u inverter

24u/.6u inveter (m=4)

Symbol view for inverters

  

 

Below includes the layout of the 12u/.6u inverter along with the DRC and LVS

 

 

 


Layout
Extracted

DRC pass

LVS pass (netlist match)

 
 
 
 Below is the layout for the 24u/2.4u inverter along with the DRC and LVS
 
 
 
 

Layout
Extracted

DRC pass

LVS pass (netlist match)

 
 
 Below are a serier of simulations to show the performance of each inverter. The pictures on the left are the 12u/.6u inverter and the pictures on the right are the 24u/2.4u inverter
 
 
12u/.6u inverter24u/2.4u inveter
    
Simulation schematic

Simulation Schematic

C=100f

C=100f

C=1p
C=1p

C=10p

C=10p

C=100p

C=100p
 From the above simulations, we can see that as the load capactiance increases, the delay on the inverter is increased. This is due to the fact that the voltage across a capacitor cannot change
instantenously. When the input switches from 0 to 5 volts, the delay time is the time it takes for the capacitor to charge nad discharge.
 
 
 
Below are the simulations using Ultrasim (cadences fast SPICE)
 
 
12u/.6u Inverter24u/2.4u inveter

C=100f
C=100f

C=1p
C=1p

C=10p
C=10p

C=100p
C=100p
 
 
 
 Lab 5 Design files
 
 
 
 
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